1. Field of the Invention
The present invention relates to a fabrication method and structure of metal interconnect, and more particularly, to a method and structure of metal interconnect using a hard mask as an etching mask and etch stop layer.
2. Description of the Prior Art
The miniaturization of semiconductor devices has achieved nanometer scale as the line width of ICs becomes smaller and smaller. When the integration of a single chip, i.e. density of semiconductor devices on a single chip, becomes bigger, it means the interval between devices becomes smaller. This presents difficulties when attempting to form contact holes and metal interconnect.
Please refer to FIGS. 1-11. FIGS. 1-11 are schematic, cross-sectional diagrams showing the process of forming contact holes and metal interconnect in accordance with a prior art method. As shown in FIG. 1, a metal-oxide-semiconductor (MOS) transistor device 20 is formed on a semiconductor substrate 10. The MOS transistor device 20, which is isolated by shallow trench isolations (STIs) 24, includes source/drain regions 12, a gate electrode 14, and a spacer structure 16 disposed on the sidewalls of the gate electrode 14. The semiconductor substrate 10 further includes a contact etch stop layer (CESL) 32 deposited over the MOS transistor device 20 and the semiconductor substrate 10, and a first dielectric layer 34 deposited on the contact etch stop layer 32. Subsequently, a bottom anti-reflective coating (BARC) layer 36 is deposited on the first dielectric layer 34. Then, a photoresist layer 40 is formed on the BARC layer 36, and a conventional exposure-and-development process is carried out to form openings 42 in the photoresist layer 40 to define the locations of contact holes to be formed later.
As shown in FIG. 2, the photoresist layer 40 is used as an etching mask to etch the exposed BARC layer 36 and the first dielectric layer 34 through the openings 42 so as to form openings 44. The etching of the first dielectric layer 34 stops on the contact etch stop layer 32. Subsequently, as shown in FIG. 3, the remaining photoresist layer 40 and the BARC layer 36 are used as an etching hard mask to etch the exposed contact etch stop layer 32 through the openings 44, thereby forming contact holes 46. As shown in FIG. 4, the remaining photoresist layer 40 and the BARC layer 36 over the first dielectric layer 34 are removed.
As shown in FIG. 5, in order to increase adhesion between metal and the first dielectric layer 34, and prevent silicide spiking and electro-migration when filling contact hole 46 with metal, a diffusion barrier layer 47, such as titanium nitride (TiN)/titanium (Ti), is required to be deposited over sidewalls of every contact hole 46 and upon gate electrode 14 and source/drain regions 12 in the bottom. Then, every contact hole 46 is filled with metal 48, such as tungsten (W), and the surface diffusion barrier layer 47 is covered with metal 48, such as tungsten (W), as shown in FIG. 6. Afterward as shown in FIG. 7, a first chemical mechanical polishing (CMP) process is proceeded to remove redundant metal 48 upon surface of the first dielectric layer 34 in order to form the required contact plug 49.
As shown in FIG. 8, an etch stop layer 50, a second dielectric layer 52, and a patterned photoresist layer 54 are deposited upon first dielectric layer 34 and contact plug 49 in sequence. The patterned photoresist layer 54 is used to as an etching mask to etch part of the second dielectric layer 52 and etch stop layer 50 to form a trench 56, as shown in FIG. 9. Subsequently, a standard copper process is carried out to deposit a diffusion barrier layer of titanium nitride (TiN)/titanium (Ti) (not shown) and a seed layer (not shown) over sidewalls of every trench 56 and upon the second dielectric layer 52 and every contact plug 49, and then electroplating is performed to form copper metal 58, as shown in FIG. 10. Finally, a second CMP process is carried out to remove redundant copper metal 58 upon the surface of second dielectric layer 52, and then metal wires 60 electrically connecting every contact plug 49 are formed separately, as shown in FIG. 11.
As mentioned above, a semiconductor contact hole process only use a photoresist pattern as an etching mask. There are more and more optical limitations of 193 nm photoresist in the lithography process, as semiconductor devices require smaller after-etch-inspection critical dimension (AEI CD) of contact holes. Therefore, in the prior art standard 65 nm contact hole process, photoresist thickness has to be lowered to 2800 angstroms in order to fabricate 65 nm contact holes in the lithography process; and in the 45 nm contact hole process, photoresist thickness has to be lowered to 2200 angstroms in the lithography process. However, excessively thin photoresist can cause boundary defects due to insufficient shielding in the etching process, so hard masks are required to be used in the etching process. Ordinary poly-silicon hard masks are not able to be used in 45 nm processes because phase variation of silicide, such as NiSi, can result.
In addition, the above-described prior art method of forming metal interconnect has another drawback: an etch stop layer is required to be deposited before forming a trench.